Integrated semiconductor memory configuration

ABSTRACT

The integrated ferroelectric or DRAM semiconductor memory configuration has memory cells each with a selection transistor and a capacitor module that can be addressed by the selection transistor. The capacitors of successive memory cells are formed alternately on the front and rear sides of a substrate wafer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention lies in the integrated technology field. Morespecifically, the invention relates to an integrated ferroelectric orDRAM semiconductor memory configuration, in which a selection transistorand a storage capacitor which can be addressed by the selectiontransistor are provided on a substrate wafer per memory cell.

[0003] A DRAM semiconductor memory configuration of this type isdisclosed in U.S. Pat. Nos. 4,959,709 and 4,978,635, and in thecorresponding German patent application DE 38 40 559 A1.

[0004] The magnitude of the switchable polarization or the charge thatcan be stored on the capacitor plates is of crucial importance for thefunctionality and also the reliability of ferroelectric memories(FeRAMS) and DRAMs having a high dielectric constant (∈). The voltage onthe bit line (BL) which is caused by the polarization or charge duringreading must not fall below a minimum value specified for the product.In the simplest case, the BL signal can be increased by enlarging thecapacitor area. However, this is accompanied by an enlargement of thechip area.

[0005] Attempts have already been made to achieve the BL signal througha suitable choice of the dielectric or ferroelectric (high dielectricconstant ∈), reduction of the thickness of the dielectric, and also bymeans of design optimizations (low BL capacitance). However,technological limits are imposed on these methods, and the conventionalpursuits therefore, lead to the enlargement of the capacitor area at theexpense of the packing density.

[0006] The semiconductor memory device disclosed in the above-notedprior art disclosures (U.S. Pat. Nos. 4,959,709, 4,978,635, and DE 38 40559 A1) above has a storage capacitor formed as a trench capacitor in atrench formed from the rear side of a silicon substrate.

SUMMARY OF THE INVENTION

[0007] It is accordingly an object of the invention to provide anintegrated ferroelectric or DRAM semiconductor memory configuration,which overcomes the above-mentioned disadvantages of theheretofore-known devices and methods of this general type and whichmakes available an enlarged capacitor area for each memory cell, andthus enables an increase in the switchable polarization or the chargethat can be stored on the capacitor plates in order to increase the BLsignal without reducing the packing density of the memory cells.

[0008] With the foregoing and other objects in view there is provided,in accordance with the invention, an integrated semiconductor memoryconfiguration, such as a ferroelectric or a DRAM memory configuration,comprising:

[0009] a substrate having a front side and a rear side;

[0010] a plurality of memory cells each having a selection transistorand a storage capacitor connected to and addressible by the selectiontransistor;

[0011] the storage capacitors of respectively successive memory cellsbeing formed alternately on the front side and the rear side of thesubstrate; and

[0012] plugs formed on the rear side of the substrate, the plugselectrically connecting an electrode region of a respective theselection transistor with a capacitor plate, facing toward the selectiontransistor, of the storage capacitor disposed on the rear side of thesubstrate.

[0013] In accordance with an added feature of the invention, the rearside of the substrate is formed with a depression and an insulatinglayer formed in the depression, and wherein the storage capacitorsformed on the rear side are disposed in the insulating layer and theinsulating layer protects the storage capacitors from an influence ofsubsequent processes.

[0014] In accordance with an additional feature of the invention, theselection transistors of the memory cells are CMOS transistors formedfrom the front side of the substrate wafer.

[0015] In accordance with a concomitant feature of the invention, thestorage capacitors formed on the front side of the substrate extend in alateral direction to partly overlap a selection transistor of theadjacent the memory cell.

[0016] In other words, every other storage capacitor is formed on therear side of the wafer. As a result, the storage capacitors can occupy alarger capacitance-forming area, which has an effective consequence interms of increasing the corresponding read signal. Moreover, plugs areformed on the rear side of the substrate wafer, which plugs electricallyconnect an electrode region of the associated selection transistor tothe capacitor plate, facing toward the selection transistor, of thestorage capacitor situated on the rear side of the substrate wafer.

[0017] By incorporating the rear side of the wafer, it is possible toachieve more effective utilization of the chip area. Consequently, withno loss of chip area, the capacitor area can be made larger than inconventional technologies in which only the front side of the wafer isutilized. By virtue of the increased BL signal, the cell size can beminiaturized still further and the reliability of the memory product canbe increased.

[0018] Applying semiconductor circuits to the front and rear sides of asilicon wafer is known, as described in German published patentapplication DE 39 14 055 A1. By means of that known two-sided process ofthe silicon wafer, however, a functionally continuous circuit is notapplied from both sides of the silicon wafer, but rather a multiplicityof circuits which are functionally isolated from one another. This isdone in the prior art in order to increase the number of semiconductorfunctions that can be realized per unit area.

[0019] Other features which are considered as characteristic for theinvention are set forth in the appended claims.

[0020] Although the invention is illustrated and described herein asembodied in an integrated semiconductor memory configuration, it isnevertheless not intended to be limited to the details shown, sincevarious modifications and structural changes may be made therein withoutdeparting from the spirit of the invention and within the scope andrange of equivalents of the claims.

[0021] The construction and method of operation of the invention,however, together with additional objects and advantages thereof will bebest understood from the following description of specific embodimentswhen read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1A is a diagrammatic section a segment of a ferroelectric orDRAM semiconductor memory configuration according to the invention; and

[0023]FIG. 1B is a diagrammatic section of an enlarged detail of thesegment of the memory configuration inside the detail line B in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Referring now to the figures of the drawing in detail and first,particularly, to FIG. 1A thereof, there is shown a cross section of asegment of a ferroelectric or DRAM semiconductor memory configuration.Insulator or barrier layers 101 and 102 are situated on the front side Vof a substrate wafer 1. Elements of the ferroelectric or DRAMsemiconductor memory configuration are provided in the layers 101, 102,such as non-illustrated interconnects, for example bit lines, plugs 17,storage capacitors 10, and non-illustrated selection transistors. Theelements are formed by a CMOS-FEOL process, for example.

[0025] A first storage capacitor 10 of a first memory cell is situatedon the front side V and the next storage capacitor 20 of the adjacentmemory cell is situated on a rear side R of the substrate wafer 1. Thefabrication of the capacitors from the front and rear sides V, R can becarried out either sequentially or by parallel processing of both sidesV and R.

[0026] In order to form the capacitors 20 on the rear side R, adepression 4 is etched from the rear side R of the substrate wafer 1 bymeans of an anisotropic etching process. A barrier layer 105 issubsequently deposited. Insulator layers 103 and 104 and a semiconductorlayer 106 are then formed in the depressions 4 on the rear side R. Thecapacitors 20 and, for electrically contact-connecting the latter to theselection transistors formed from the front side V, plugs 7 are formedin said layers 103 and 104. The plugs 7 pass through the barrier layer105 right into the layer 101 containing the CMOS selection transistors.

[0027] A commonly assigned German patent application, DE 100 65 669,entitled “Method for fabricating an integrated semiconductor memoryconfiguration” and filed concurrently with the German application uponwhich priority under § 119 is claimed herein, relates to a method forfabricating an integrated semiconductor memory configuration. That textdescribes details of a fabrication process of storage capacitors forferroelectric memories or DRAM memories on the rear side of the wafer.It is explained for the fabrication process described therein, too, thatthe storage capacitors can be fabricated on the front and rear sides ofthe substrate wafer either sequentially or by parallel processing ofboth sides of the wafer, in which case, in the case of parallelprocessing of both sides of the wafer, as many layers and elements aspossible are formed simultaneously on both sides of the wafer. Thedisclosure of that application is herein incorporated by reference.

[0028] The detail B of FIG. 1A which is illustrated enlarged in FIG. 1Bshows that the capacitors 10, 20 which are formed on the front and rearsides V, R of the wafer 1 and are connected to selection transistors 2and 3 by the plugs 17 and 7 in each case have capacitor plates 11, 13and 21, 23, respectively, and intervening dielectric or ferroelectriclayers 12 and 22, respectively. FIG. 1B clearly shows that, by virtue ofthe formation of every second capacitor 20 on the rear side R of thewafer, with no loss of chip area, the capacitor area can be made largerthan in conventional technology in which only the front side of thewafer is utilized. The capacitor 10 formed on the front side V extendsso far in the lateral direction that it overlaps the selectiontransistor 3 of the next memory cell, which selection transistor isformed in the semiconductor layer 106. The same applies to the capacitor20 which is formed from the rear side R and can extend in the lateraldirection right into the vicinity of the next capacitor formed from therear side R.

[0029] The enlarged illustration in FIG. 1B also shows the plugs 17 and7 formed for the purpose of connecting the capacitor plates 11 and 21,respectively, to an n+-type transistor region of the selectiontransistors 2 and 3 situated in the semiconductor layer 106, of whichplugs the plug 17 is formed from the front side V and the plug 7 isformed from the rear side R of the substrate wafer 1. Further plugs 5serve for connecting the respective other transistor electrodes of theselection transistors 2 and 3 to a non-illustrated metallization planecontaining the bit lines.

[0030] The proposed measure of forming every other storage capacitor 20on the rear side of the substrate wafer 1 yields a larger bit linesignal, which contributes to a further reduction of the area of the celland increases the reliability of the memory product.

We claim:
 1. An integrated semiconductor memory configuration,comprising: a substrate having a front side and a rear side; a pluralityof memory cells each having a selection transistor and a storagecapacitor connected to and addressible by said selection transistor;said storage capacitors of respectively successive memory cells beingformed alternately on said front side and said rear side of saidsubstrate; and plugs formed on said rear side of said substrate, saidplugs electrically connecting an electrode region of a respective saidselection transistor with a capacitor plate, facing toward saidselection transistor, of said storage capacitor disposed on said rearside of said substrate.
 2. The integrated semiconductor memoryconfiguration according to claim 1, wherein said memory cells areferroelectric memory cells.
 3. The integrated semiconductor memoryconfiguration according to claim 1, wherein said memory cells are DRAMcells.
 4. The integrated semiconductor memory configuration according toclaim 1, wherein said rear side of said substrate is formed with adepression and an insulating layer formed in said depression, andwherein said storage capacitors formed on said rear side are disposed insaid insulating layer and said insulating layer protects said storagecapacitors from an influence of subsequent processes.
 5. The integratedsemiconductor memory configuration according to claim 1, wherein saidselection transistors of said memory cells are CMOS transistors formedfrom said front side of said substrate wafer.
 6. The integratedsemiconductor memory configuration according to claim 1, wherein saidstorage capacitors formed on said front side of said substrate extend ina lateral direction to partly overlap a selection transistor of theadjacent said memory cell.